KiCad MCP Pro
v3.25.0Local MCP based on oaslananka/kicad-mcp-pro covering project setup, schematic/PCB read-write, ERC/DRC, DFM, SI/PI helpers, SPICE, and manufacturing exports (Gerber/BOM/STEP). Prefer uvx; requires KiCad installed (10.x recommended) with its bin on PATH. The tool surface is large — this page curates common capabilities; see upstream docs for the full catalog.
§ Quickstart
Add the following to your MCP client configuration (Cursor, Claude Desktop, etc.):
Launch kicad-mcp-pro from PyPI via uvx. Replace the project path with your absolute path and keep KiCad bin on PATH.
On Windows, ensure PATH includes KiCad 10 bin (e.g. C:\Program Files\KiCad\10.0\bin). Use profiles like pcb_only / schematic_only to shrink the tool surface.
MCP Client Configuration
{
"mcpServers": {
"kicad-mcp-pro": {
"command": "uvx",
"args": [
"kicad-mcp-pro"
],
"env": {
"KICAD_MCP_PROJECT_DIR": "C:\\path\\to\\your\\kicad-project",
"KICAD_MCP_PROFILE": "full",
"KICAD_MCP_OPERATING_MODE": "write"
}
}
}
}Config file locations
- Cursor: Settings → MCP, or edit ~/.cursor/mcp.json
- Claude Desktop: edit claude_desktop_config.json (macOS: ~/Library/Application Support/Claude/, Windows: %APPDATA%\Claude\)
§ Tools Reference
11 tools
kicad_set_project
Bind the active KiCad project path
| Parameter | Type | Required | Description |
|---|---|---|---|
| project_path | string | ✓ | Project directory or .kicad_pro path |
project_get_design_spec
Read project design spec / design intent
sch_get_symbols
List schematic symbols and key properties
sch_trace_net
Trace schematic connectivity by net name
| Parameter | Type | Required | Description |
|---|---|---|---|
| net | string | ✓ | Net name |
pcb_get_board_summary
Get PCB board summary (size, layers, footprint counts, etc.)
run_drc
Run PCB Design Rule Check (DRC)
run_erc
Run schematic Electrical Rule Check (ERC)
export_bom
Export Bill of Materials (BOM)
export_gerber
Export Gerber / drill manufacturing files
dfm_run_manufacturer_check
Run DFM checks against a manufacturer profile
project_quality_gate
Run project-level quality gate summary
§ Examples
Once configured, you can ask the AI directly:
Bind project and run quality gate
Set the project to my board folder, read the design spec, run project_quality_gate, and summarize failures in English.
Typical connect-then-validate kickoff.
DRC + manufacturing export
Run DRC on the current PCB; if clean, export Gerber and BOM and report the output folder.
Pre-release check and handoff artifacts.
Trace a net
Trace schematic net VCC_3V3 and list related symbols and pins.
Connectivity investigation.
LadleAgent